The layout of an IC must not only satisfy geometric requirements, e.g., non-overlapping cells and routability, but also meet the design's timing constraints, e.g., setup (long-path) and hold (short-path) constraints. The optimization process that meets these requirements and constraints is often called timing closure. Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation in order to perform timing closure. STA has been a typical analysis algorithm for the design of IC chips over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis (SSTA), which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.
Statistical static timing analysis (SSTA) may be performed for final timing closure or timing signoff using a first-order linear approximation of a Taylor series, referred to as a canonical model. However, if a range for a parameter (e.g., voltage) of the canonical model increases, then non-linearity or second order error may be introduced into the canonical model. Moreover, at least two unique timing runs (e.g., SSTA) are typically required and each of the timing runs should assert a perfect correlation between at least two parameters in order to provide timing within a process subspace.
SSTA may also be performed for final timing closure or timing signoff using an nth-order extension (e.g., a second-order extension) of the aforementioned first-order linear approximation. More specifically, nth order cross terms (e.g., second order cross terms) for at least two parameters may be incorporated into the first order approximation of the Taylor series, referred to as an extended canonical model. This timing closure typically only requires a single timing run (e.g., SSTA) because it includes the cross terms to span the extended parameter range. However, this form of timing closure typically reduces coverage to a significantly reduced process subspace.